Finally It Is Done!:)

This summer I had to pass my practical course. Although my the boss was the friend of my father's friend's friend, it does not mean that my work was going to be wasn't that much easy. Even though I didn't don't have to go to be in the office but I do have had some projects to do in at home instead.

I had to write a Verilog code in Verilog, a Matlab code language and to create a "simulink" in Matlab, based on my Matlab code. I also had to use the HDL coder in the simulink and to generate automatic Verilog code by that tool. At the end Finally, I had to compare my Verilog code generation with those of code's result and Simulink's Verilog code's result to recognize to see if there are any difference.

At first Initially, I thought this project must have been too easy, is a piece of cake but when I started, I faced there were many difficulties and obstacles!! A lot of difficulties Much of it has to do with Matlab's Simulink and it's limitations! I should also confess that I'm am a bit lazy :P , but that again this is no easy project wasn't really that much easy!:D

During my practical course I had to learn the VHDL language too. I studied did some tutorials but there was no one to help me on that. I figured out some things but I didn't did not have enough self-confidence to write my program in VHDL instead of using Verilog. ! I dunno am not sure if my boss accepts my work in this way. [Your mistake is in not asking.  If you are not sure, ask, ask and ask.  My staff will be in very hot water if they don't ask when they are not sure of things.  I don't want them to second guess me but they ARE always welcome to verify with me their assumptions. This is being proactive and does not reflect on their competence.  Prevention is better than cure.] without learning VHDL completely at the end or not!

I almost did everything achieved most of what I set out I was wanted to do. I dunno don't know wheather it this is enough for my professor [not abbreviations!] to pass me or not.  but However, now I'm so happy now that I have finally completed all this. finished that! Some days, it was like a nightmare for me in some days. I hope it would be OK at last! :) that everything turns out well.

Finally, It Is Done!:)

This summer, I had to pass my practical course. Although my boss was my father's friend's friend, my work wasn't that much easy. I didn't have to go to the office but I had some project to do in home instead.

I had to write a Verilog code, a Matlab code and create a Simulink in Matlab, based on my Matlab code. I also had to use the HDL coder in simulink and generate a Verilog code by that tool. At the end, I had to compare my Verilog code's result and Simulink's Verilog code's result to recognize any difference.

At first, I thought this project must have been too easy, but when I started, I faced many difficulties!! A lot of difficulties with Matlab's Simulink and its limitations! I should confess that I'm a bit lazy, :P , but that project wasn't really that much easy!:D

During my practical course, I had to learn VHDL language too. I studied some tutorials but there was no one to help me on that. I figured out some things but I didn't have enough self-confidence to write my program in VHDL instead of Verilog! I dunno (dont know) if my boss accepts my work without learning VHDL completely at the end or not!

I almost did everything I was expected to do. I dunno whether it is enough for my professor to pass me or not, but now I'm so happy now that I finally finished that! It was like a nightmare for me in some days. I hope it would be fine at last! :)